Field-programmable gate array
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FPGAs should not be confused with the flip-chip pin grid array, a form of integrated circuit packaging.
An Altera Stratix II GX FPGA.A field-programmable gate array is a semiconductor device containing programmable logic components called "logic blocks", and programmable interconnects. Logic blocks can be programmed to perform the function of basic logic gates such as AND, and XOR, or more complex combinational functions such as decoders or mathematical functions. In most FPGAs, the logic blocks also include memory elements, which may be simple flip-flops or more complete blocks of memory.
A hierarchy of programmable interconnects allows logic blocks to be interconnected as needed by the system designer, somewhat like a one-chip programmable breadboard. Logic blocks and interconnects can be programmed by the customer or designer, after the FPGA is manufactured, to implement any logical function—hence the name "field-programmable".
FPGAs are usually slower than their application-specific integrated circuit (ASIC) counterparts, cannot handle as complex a design, and draw more power (for any given semiconductor process). But their advantages include a shorter time to market, ability to re-program in the field to fix bugs, and lower non-recurring engineering costs. Vendors can sell cheaper, less flexible versions of their FPGAs which cannot be modified after the design is committed. The designs are developed on regular FPGAs and then migrated into a fixed version that more resembles an ASIC.
"Complex Programmable Logic Device" (CPLDs) are an alternative for simpler designs. They also retain their programming over powerdowns.
To configure ("program") an FPGA or CPLD you specify how you want the chip to work with a logic circuit diagram or a source code using a hardware description language (HDL). The HDL form might be easier to work with when handling large structures because it's possible to just specify them numerically rather than having to draw every piece by hand. On other hand schematic entry might allow for more tight specification of what you want.
Going from schematic/HDL source files to actual configuration: The source files are fed to a software suite from the FPGA/CPLD vendor that through different steps will produce a file. This file is then transferred to the FPGA/CPLD via a serial interface (JTAG) interface or to external memory device like an EEPROM.
Contents [hide]
1 History
2 Modern developments
3 Soft Processors
4 Applications
5 Architecture
6 FPGA design and programming
7 Basic process technology types
8 Manufacturers and their specialties
9 See also
10 Notes
11 External links
11.1 Resources
11.2 Software Tools
11.3 Media
[edit] History
The historical roots of FPGAs are in complex programmable logic devices (CPLDs) of the early to mid 1980s. A Xilinx co-founder, Ross Freeman, invented the field programmable gate array in 1984. CPLDs and FPGAs include a relatively large number of programmable logic elements. CPLD logic gate densities range from the equivalent of several thousand to tens of thousands of logic gates, while FPGAs typically range from tens of thousands to several million.
The primary differences between CPLDs and FPGAs are architectural. A CPLD has a somewhat restrictive structure consisting of one or more programmable sum-of-products logic arrays feeding a relatively small number of clocked registers. The result of this is less flexibility, with the advantage of more predictable timing delays and a higher logic-to-interconnect ratio. The FPGA architectures, on the other hand, are dominated by interconnect. This makes them far more flexible (in terms of the range of designs that are practical for implementation within them) but also far more complex to design for.
Another notable difference between CPLDs and FPGAs is the presence in most FPGAs of higher-level embedded functions (such as adders and multipliers) and embedded memories.
Some FPGAs have the capability of partial re-configuration that lets one portion of the device be re-programmed while other portions continue running.
[edit] Modern developments
A recent trend has been to take the coarse-grained architectural approach a step further by combining the logic blocks and interconnects of traditional FPGAs with embedded microprocessors and related peripherals to form a complete "system on a programmable chip". Examples of such hybrid technologies can be found in the Xilinx Virtex-II PRO and Virtex-4 devices, which include one or more PowerPC processors embedded within the FPGA's logic fabric. The Atmel FPSLIC is another such device, which uses an AVR processor in combination with Atmel's programmable logic architecture.
An alternate approach to using hard-macro processors is to make use of "soft" processor cores that are implemented within the FPGA logic. (See "Soft processors" below).
As previously mentioned, many modern FPGAs have the ability to be reprogrammed at "run time," and this is leading to the idea of reconfigurable computing or reconfigurable systems — CPUs that reconfigure themselves to suit the task at hand. The Mitrion Virtual Processor from Mitrionics is an example of a reconfigurable soft processor that is implemented on FPGAs. It does not however support dynamic reconfiguration at runtime, but instead adapts itself to a specific program.
It has been suggested that this article or section be merged into soft microprocessor. (Discuss)
Additionally, new, non-FPGA architectures are beginning to emerge. Software-configurable microprocessors such as the Stretch S5000 adopt a hybrid approach by providing an array of processor cores and FPGA-like programmable cores on the same chip.
[edit] Soft Processors
Main article: soft microprocessor
There are many soft microprocessor cores available, both closed and open source. For a given CPU architecture, a hard (embedded) CPU core will outperform a soft-core CPU (i.e., a programmable-logic implementation of the CPU). The following list is by no means exhaustive.
Processor Developer Source code Bus support Notes Project home
Nios, Nios II Altera available under Altera license Avalon, Wishbone 32-bit RISC architecture Altera Nios II
TSK3000 Altium Closed, Royalty free WishBone 32-bit RISC Modified Harvard architecture Altium TSK3000
TSK51x/52x Altium Closed, Royalty free WishBone/80C51 8-bit 80C51 compatible, outperforms most 80C51 derivatives TSK51x TSK52x
TSK80 Altium Closed, Royalty free Z80 bus 8-bit optimized Z80 instruction set compatible TSK80
Mico32 Lattice open source Wishbone LatticeMico32
PacoBlaze Pablo Bleyer open source Compatible with the PicoBlaze processors PacoBlaze
AEMB Shawn Tan yes Wishbone MicroBlaze EDK 3.2 compatible Verilog core AEMB
Diamond 106Micro Tensilica available under Tensilica license PIF, AHB Lite, AXI 32-bit RISC architecture Tensilica Diamond 106Micro
OpenFire Virginia Tech CCM Lab open source OPB, FSL Binary compatible with the MicroBlaze VT OpenFire
MicroBlaze Xilinx available under Xilinx license OPB, FSL, LMB, PLB Xilinx MicroBlaze
PicoBlaze Xilinx available under Xilinx license Xilinx PicoBlaze
[edit] Applications
Applications of FPGAs include digital signal processing, software-defined radio, aerospace and defense systems, ASIC prototyping, medical imaging, computer vision, speech recognition, cryptography, bioinformatics, computer hardware emulation and a growing range of other areas. FPGAs originally began as competitors to CPLDs and competed in a similar space, that of glue logic for PCBs. As their size, capabilities, and speed increased, they began to take over larger and larger functions to the state where some are now marketed as full systems on chips (SOC).
FPGAs especially find applications in any area or algorithm that can make use of the massive parallelism offered by their architecture. One such area is code breaking, in particular brute-force attack, of cryptographic algorithms.
FPGAs are increasingly used in conventional High Performance Computing applications where computational kernels such as FFT or Convolution are performed on the FPGA instead of a microprocessor. The use of FPGAs for computing tasks is known as reconfigurable computing.
The inherent parallelism of the logic resources on the FPGA allows for considerable compute throughput even at a sub-500 MHz clock rate. For example, the current (2007) generation of FPGAs can implement around 100 single precision floating point units, all of which can compute a result every single clock cycle. The flexibility of the FPGA allows for even higher performance by trading off precision and range in the number format for an increased number of parallel arithmetic units. This has driven a new type of processing called reconfigurable computing, where time intensive tasks are offloaded from software to FPGAs.
The adoption of FPGAs in high performance computing is currently limited by the complexity of FPGA design compared to conventional software and the extremely long turn-around times of current design tools, where 4-8 hours wait is necessary after even minor changes to the source code.
